In many electronics applications, an analog input signal is converted to a digital output signal (e.g., for further digital signal processing). For instance, in precision measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors may generate an analog signal. The analog signal would then be provided to an analog-to-digital converter (ADC) as input to generate a digital output signal for further processing. In another instance, in a mobile device receiver, an antenna generates an analog signal based on the electromagnetic waves carrying information/signals in the air. The analog signal generated by the antenna is then provided as input to an ADC to generate a digital output signal for further processing.
Analog-to-digital converters (ADCs) based on delta-sigma (ΔΣ) modulation (referred to herein as “ΔΣ modulators” or “ΔΣ ADCs” interchangeably) have been widely used in digital audio and high precision instrumentation systems. ΔΣ modulators usually provides the advantage of being able to convert an analog input signal to a digital signal with high resolution at low cost. Typically, a ΔΣ ADC encodes an analog signal using a ΔΣ modulator (e.g., using a low resolution ADC such as a 1-bit ADC, Flash ADC, Flash quantizer etc.) and then, if applicable, applies a digital filter to the output of the ΔΣ modulator to form a higher-resolution digital output. A loop filter may be provided to provide error feedback the ΔΣ modulator. One key characteristic of a ΔΣ modulator is its ability to push the quantization noise to higher frequencies, also referred to as noise shaping. As a result, ΔΣ ADCs are generally able to achieve high resolution analog-to-digital conversion. Due to its popularity, many variations on the ΔΣ ADC and structures employing the ΔΣ ADC have been proposed.
Overview
The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.